How to Use make and makefile in Linux

make

One of the main reasons why Linux is popular among C/C++ programmers is the support provided by Linux to them. This includes the g++ compiler suite and its related tools used for program development such as the make command.

In this tutorial, you will learn about the make command in Linux, its use, the basis of the makefile, and how it is used with the make command.

What is the make command?

Large and complex software applications consist of hundreds of source code and other files. Compiling and linking these files is not easy and can be erroneous. During the build process of these applications, several object files are also created. To manage these files and the entire software development project, the make command is used in Linux.

Consider the case when the programmers have their projects in simple folders. They don’t have any IDE (Integrated Development Environment) such as Eclipse or Visual Studio available to compile and handle their project. The only available option is to use the terminal to compile the source code. Instead of remembering all the commands to compile their files manually, or keeping track of files that are changed and need to be recompiled, they can simply use the make command to handle things for them automatically.

Instead of performing the compilation steps individually and remembering the file names and commands, the make command can be used to automatically perform these tasks. In short, make allows you to automatically build, compile, execute or even install complex software applications using a single command. Thus, it makes the life of a C/C++ programmer easier.

Makefile

The basis of the make command is a text file called Makefile. The Makefile contains the instructions regarding options passed to the compiler.

Makefile is usually created as a text file without any extension, like this

touch makefile 

In this file, you can write a set of commands to perform various tasks. For example,

g++ main.cpp -o example_code

./example_code

 

You can consider Makefile as a simple bash script that contains commands to build, compile, and run your code files. Now if you enter the make command like this

make

it will execute the instructions (commands) written in the Makefile. In the example given above, it will first compile the main.cpp file and will create an executable file named ‘example_code’, then it will execute the ‘example_code’ file.

In this way, you can write multiple commands in the Makefile and execute them all using the simple make command.

Wait, you might be thinking that a Makefile is just like a simple bash script, so what is the big deal? No, the make command can do more than what you just thought, so keep on reading.

Structure of a Makefile

You can set up several targets in a Makefile, which you can then use with the make command. A target can be specified by writing its name followed by a colon (:), for example,

all:

g++ main.cpp -o example_code

run:

./example_code

 

here ‘all’ and ‘run’ are targets. By default, the make command will execute the instructions written after the first target (‘all’ in this case).

If you want to execute instructions written after a specific target, you have to specify its name, for example,

make run

This command will run the executable ‘example_code’, as mentioned after the target ‘run’ in the above example.

File dependency

The other important thing you can specify in a Makefile is file dependency. It means that Makefile can specify the code modules which are required to build the program. In addition, it can also specify the required source code files for a particular code module. Therefore, you can use a Makefile for dependency checking.

In a Makefile, you can specify a dependency after the target name is separated by a space, like this

main.o: main.cpp

The above line says that the object file ‘main.o’ has a dependency on ‘main.cpp’. In other words, to execute this target the ‘main.cpp’ must exist.

Using make command to delete files

You can use the make command to delete all object and executable files created during the build process. For that, you have to create a target in the Makefile similar to the example given below.

clean:

'rm -rf *o example_code'

 

this target when executed (using $ make clean) will delete all object files and the executable named ‘example_code’.

The use of variables

You can declare and use variables in a Makefile to represent values that might change. For instance, you can represent the name of the compiler using a variable like this

CC=g++

Suppose you want to change the compiler (say to gcc), then you need to change only this value if you are using a variable. There would be no need to change it in all the occurrences in the Makefile because there the name of the variable is used.

$(CC) main.cpp

You can see a variable is specified with the help of a $ sign. You can also specify options using variables, like

FLAGS= -c -Wall

And then use them as shown below:

$(CC) $(FLAGS) main.cpp

Remember before using the make command

  • The make command can be used with a simple Makefile or with complex Makefiles containing several macros or commands. The use of macros with the make command brings application portability. It means the application can be used on other operating systems.
  • If no file is specified, the default Makefile will be used. If you want to use your Makefile then you have to specify its name using the -f option.
make -f MyFile
  • The make command can also be used to install a program. For that you need to specify a target in the Makefile, mentioning the program and pathname in the install command, like the one shown below:

install: skel

install -g root -o root skel /usr/local/bin

Now, it is also possible to build and install a program in a single step (i.e., by executing the make command). If you want only installation, you can use the following command.

make install
  • If you change any element of a target (such as a source code file), the make command will rebuild the target automatically.

Advantages

Here are some advantages of the make command and the Makefile, which will show you, its importance.

  • It makes the codes easier and clearer to read and removes errors from them.
  • If you make any changes in the program files, you do not need to compile them again and again. Instead, the make command will automatically compile those files only where changes have been done.
  • Makefile is also used to present a project in a more systematic, organized, and efficient way. You can divide a large application program into smaller parts and use the Makefile to handle these smaller parts in different ways.
  • Make command allows us to compile multiple files at once so that all the files can be compiled in a single step which is time-efficient as well.
  • In the case of compiling multiple files, there is no need to type the names of all the files at the command prompt. Remembering their names is difficult and typing their names can be an error-prone task. So, it is easy to write their names once in the Makefile and let the make command handle everything.

Conclusion

In this tutorial, you have studied the make command and Makefile in detail. The make command is used to manage large development projects comprising of tens of source code files. The Makefile is simply a text file that is being used by the make command to set up targets. It allows us to represent the whole project systematically and efficiently thereby making it easier and more readable to debug.

 

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